Technical Field
The present invention relates to integrated circuits, and more particularly to three-dimensional integrated circuit inductor structures configured with lateral and/or vertical equal path length architectures.
Description of the Related Art
With an increased demand for personal mobile communications, integrated semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices may, for example, include voltage controlled oscillators (VCO), low noise amplifiers (LNA), tuned radio receiver circuits, or power amplifiers (PA). Each of these tuned radio receiver circuits, VCO, LNA, and PA circuits may, however, require on-chip inductor components in their circuit designs.
Several design considerations associated with forming on-chip inductor components may, for example, include quality factor (i.e., Q-factor), self-resonance frequency (fSR), and cost considerations impacted by the area occupied by the formed on-chip inductor. Accordingly, for example, a 7CMOS radio frequency (RF) circuit design may benefit from, among other things, one or more on-chip inductors having a high Q-factor, a small occupied chip area, and a high fSR value. The fSR of an inductor may be given by the following equation:
            f      SR        =          1              2        ⁢        π        ⁢                  LC                      ,where L is the inductance value of the inductor and C may be the capacitance value associated with the inductor coil's inter-winding capacitance, the inductor coil's interlayer capacitance, and the inductor coil's ground plane (i.e., chip substrate) to coil capacitance. From the above relationship, a reduction in capacitance C may desirably increase the fSR of an inductor. One method of reducing the coil's ground plane to coil capacitance (i.e., metal to substrate capacitance) and, therefore, C value, is by using a high-resistivity semiconductor substrate such as a silicon-on-insulator (SOI) substrate. By having a high resistivity substrate (e.g., >50 Ω-cm), the effect of the coil's metal (i.e., coil tracks) to substrate capacitance is diminished, which in turn may increase the fSR of the inductor. Reducing the inductor coil's inter-winding and interlayer capacitance can similarly increase the fSR of the inductor.
The Q-factor of an inductor at frequencies well below fSR may be given by the equation:
      Q    =                  ω        ⁢                                  ⁢        L            R        ,where ω is the angular frequency, L is the inductance value of the inductor, and R is the resistance of the coil. As deduced from the above relationship, a reduction in coil resistance may lead to a desirable increase in the inductor's Q-factor. For example, in an on-chip inductor, by increasing the turn-width (i.e., coil track width) of the coil, R may be reduced in favor of increasing the inductors Q-factor to a desired value. In radio communication applications, the Q-factor value is set to the operating frequency of the communication circuit. For example, if a radio receiver is required to operate at 2 GHz, the performance of the receiver circuit may be optimized by designing the inductor to have a peak Q frequency value of about 2 GHz. The fSR and Q-factor of an inductor are directly related in the sense that by increasing fSR, peak Q is also increased.
Skin effect is the tendency for high-frequency currents to flow on the surface of a conductor. Proximity effect is the tendency for current to flow in other undesirable patterns, e.g., loops or concentrated distributions, due to the presence of magnetic fields generated by nearby conductors. In transformers and inductors, proximity effect losses typically dominate over skin effect losses. Proximity and skin effects significantly complicate the design of efficient transformers and inductors operating at high frequencies.
In radio frequency tuned circuits used in radio equipment, proximity and skin effect losses in the inductor reduce the Q factor. To minimize this, special construction is used in radio frequency inductors. The winding is usually limited to a single layer, and often the turns are spaced apart to separate the conductors. In multilayer coils, the successive layers are wound in a crisscross pattern to avoid having wires lying parallel to one another.